
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   12:45:56 03/10/2012
-- Design Name:   IOInterface
-- Module Name:   C:/Prog/CUARTO/AIC/CycloneProject/procesadorcyclone-aic-uspceu-2011-2012/ES/tb_IOInterface.vhd
-- Project Name:  entradaSalida
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: IOInterface
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use work.definitions.all;

ENTITY tb_IOInterface_vhd IS
END tb_IOInterface_vhd;

ARCHITECTURE behavior OF tb_IOInterface_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT IOInterface
	PORT(
	
		instr_ack_i : IN std_logic;
		instr_word_i : IN std_logic_vector(17 downto 0);
		data_ack_i : IN std_logic;
		data_word_i : IN std_logic_vector(7 downto 0);
		port_ack_i : IN std_logic;
		port_word_i : IN std_logic_vector(7 downto 0);
		cu_status : IN state_type;
		cu_mem_op : IN std_logic;
		ena_mem_port_data : IN std_logic;
		mem_rw : IN std_logic;
		datapath_word_o : IN std_logic_vector(7 downto 0);
		datapath_addr_o : IN std_logic_vector(7 downto 0);
		pc : IN std_logic_vector(9 downto 0);          
		instr_reg : OUT std_logic_vector(17 downto 0);
		data_reg : OUT std_logic_vector(7 downto 0);
		instr_cyc_o : OUT std_logic;
		instr_stb_o : OUT std_logic;
		instr_addr_o : OUT std_logic_vector(9 downto 0);
		data_cyc_o : OUT std_logic;
		data_stb_o : OUT std_logic;
		data_we_o : OUT std_logic;
		data_addr_o : OUT std_logic_vector(7 downto 0);
		data_word_o : OUT std_logic_vector(7 downto 0);
		port_cyc_o : OUT std_logic;
		port_stb_o : OUT std_logic;
		port_we_o : OUT std_logic;
		port_addr_o : OUT std_logic_vector(7 downto 0);
		port_word_o : OUT std_logic_vector(7 downto 0);
		instr_ack_to_cu : OUT std_logic;
		data_ack_to_cu : OUT std_logic;
		port_ack_to_cu : OUT std_logic
		);
	END COMPONENT;

	--Inputs
	SIGNAL instr_ack_i :  std_logic := '0';
	SIGNAL data_ack_i :  std_logic := '0';
	SIGNAL port_ack_i :  std_logic := '0';
	signal cu_status : state_type:= WRITEBACK;
	SIGNAL cu_mem_op :  std_logic := '0';
	SIGNAL ena_mem_port_data :  std_logic := '0';
	SIGNAL mem_rw :  std_logic := '0';
	SIGNAL instr_word_i :  std_logic_vector(17 downto 0) := (others=>'0');
	SIGNAL data_word_i :  std_logic_vector(7 downto 0) := (others=>'0');
	SIGNAL port_word_i :  std_logic_vector(7 downto 0) := (others=>'0');
	SIGNAL datapath_word_o :  std_logic_vector(7 downto 0) := (others=>'0');
	SIGNAL datapath_addr_o :  std_logic_vector(7 downto 0) := (others=>'0');
	SIGNAL pc :  std_logic_vector(9 downto 0) := (others=>'0');

	--Outputs
	SIGNAL instr_reg :  std_logic_vector(17 downto 0);
	SIGNAL data_reg :  std_logic_vector(7 downto 0);
	SIGNAL instr_cyc_o :  std_logic;
	SIGNAL instr_stb_o :  std_logic;
	SIGNAL instr_addr_o :  std_logic_vector(9 downto 0);
	SIGNAL data_cyc_o :  std_logic;
	SIGNAL data_stb_o :  std_logic;
	SIGNAL data_we_o :  std_logic;
	SIGNAL data_addr_o :  std_logic_vector(7 downto 0);
	SIGNAL data_word_o :  std_logic_vector(7 downto 0);
	SIGNAL port_cyc_o :  std_logic;
	SIGNAL port_stb_o :  std_logic;
	SIGNAL port_we_o :  std_logic;
	SIGNAL port_addr_o :  std_logic_vector(7 downto 0);
	SIGNAL port_word_o :  std_logic_vector(7 downto 0);
	SIGNAL instr_ack_to_cu :  std_logic;
	SIGNAL data_ack_to_cu :  std_logic;
	SIGNAL port_ack_to_cu :  std_logic;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: IOInterface PORT MAP(
		instr_ack_i => instr_ack_i,
		instr_word_i => instr_word_i,
		data_ack_i => data_ack_i,
		data_word_i => data_word_i,
		port_ack_i => port_ack_i,
		port_word_i => port_word_i,
		cu_status => cu_status,
		cu_mem_op => cu_mem_op,
		ena_mem_port_data => ena_mem_port_data,
		mem_rw => mem_rw,
		datapath_word_o => datapath_word_o,
		datapath_addr_o => datapath_addr_o,
		pc => pc,
		instr_reg => instr_reg,
		data_reg => data_reg,
		instr_cyc_o => instr_cyc_o,
		instr_stb_o => instr_stb_o,
		instr_addr_o => instr_addr_o,
		data_cyc_o => data_cyc_o,
		data_stb_o => data_stb_o,
		data_we_o => data_we_o,
		data_addr_o => data_addr_o,
		data_word_o => data_word_o,
		port_cyc_o => port_cyc_o,
		port_stb_o => port_stb_o,
		port_we_o => port_we_o,
		port_addr_o => port_addr_o,
		port_word_o => port_word_o,
		instr_ack_to_cu => instr_ack_to_cu,
		data_ack_to_cu => data_ack_to_cu,
		port_ack_to_cu => port_ack_to_cu
	);

	tb : PROCESS 
	BEGIN
		
		cu_status <= FETCH;
		pc<="0000000001";
		cu_status<=FETCH; 
		wait for 100 ns; -- respuesta de la memoria
		instr_ack_i <= '1';
		instr_word_i <="000000000000000001";
		
		wait for 100 ns;
		instr_ack_i <= '0'; --FIN CICLO MEMORIA
		
		
		
		-- Decode
		cu_status <= DECODE;
		wait for 200 ns;	

		-- EXECUTE
		cu_mem_op <='1';
		cu_status <= EXECUTE;
		mem_rw <='0';
		ena_mem_port_data <= '0';
		datapath_addr_o <= "11100000";
		wait for 100 ns;  --Comienzo respuesta memoria
		data_word_i<= "11110000";
		data_ack_i<='1';
		wait for 100 ns;
		data_ack_i<='0';  --Fin respuesta memoria
		
			
		-- WB
		cu_mem_op <='0';
		cu_status <= WRITEBACK;
		wait for 200 ns;
		
		
		
		
		
		-- Wait 100 ns for global reset to finish
--		wait for 100 ns;
--		instr_ack_i<='0';
--		instr_word_i<="XXXXXXXXXXXXXXXXXX";
--		pc<="XXXXXXXXXX";
--		cu_status <= WRITEBACK;
--		
--		wait for 100 ns; --Test del fetch
--		pc<="0000000001";
--		cu_status<=FETCH; 
--		wait for 100 ns; -- respuesta de la memoria
--		instr_ack_i <= '1';
--		instr_word_i <="000000000000000001";
--		wait for 100 ns;
--		instr_ack_i <= '0'; --FIN CICLO MEMORIA
--		wait for 100 ns;
--		pc<="0000000011";
--		cu_status<=DECODE;
--		wait for 100 ns; 
--		--pc<="0000000011";
--		cu_status<=EXECUTE;
--		
--		wait for 100 ns; --Test de lectura de DATA
--		--pc<="0000000011";
--		cu_status<=MEM;
--		mem_rw <='0';
--		ena_mem_port_data <= '0';
--		datapath_addr_o <= "11100000";
--		wait for 100 ns;  --Comienzo respuesta memoria
--		data_word_i<= "11110000";
--		data_ack_i<='1';
--		wait for 100 ns;
--		data_ack_i<='0';  --Fin respuesta memoria
--		wait for 100 ns;
--		cu_status <= WRITEBACK;
--		
--			wait for 100 ns; --Test de lectura de PORT
--		--pc<="0000000011";
--		cu_status<=MEM;
--		mem_rw <='0';
--		ena_mem_port_data <= '1';
--		datapath_addr_o <= "11100111";
--		wait for 100 ns;  --Comienzo respuesta memoria
--		port_word_i<= "00001111";
--		port_ack_i<='1';
--		wait for 100 ns;
--		port_ack_i<='0';  --Fin respuesta memoria
--		wait for 100 ns;
--		cu_status <= WRITEBACK;
--		
--		wait for 100 ns; --Test de escritura de DATA
--		--pc<="0000000011";
--		cu_status<=MEM;
--		mem_rw <='1';
--		ena_mem_port_data <= '0';
--		datapath_addr_o <= "11100100";
--		datapath_word_o <= "11100110";
--		wait for 100 ns;  --Comienzo respuesta memoria
--		data_ack_i<='1';
--		wait for 100 ns;
--		data_ack_i<='0';  --Fin respuesta memoria
--		wait for 100 ns;
--		cu_status <= WRITEBACK;
--		
--		wait for 100 ns; --Test de escritura de PORT
--		--pc<="0000000011";
--		cu_status<=MEM;
--		mem_rw <='1';
--		ena_mem_port_data <= '1';
--		datapath_addr_o <= "11101010";
--		datapath_word_o <= "11101110";
--		wait for 100 ns;  --Comienzo respuesta memoria
--		port_ack_i<='1';
--		wait for 100 ns;
--		port_ack_i<='0';  --Fin respuesta memoria
--		wait for 100 ns;
--		cu_status <= WRITEBACK;		
		
		
		-- Place stimulus here

		wait; -- will wait forever
	END PROCESS;

END;
